Researchers Reduce Contact Resistance in 2D Transistors for Advanced CMOS

Semiconductor Engineering reported that researchers at Huazhong University of Science and Technology, Hong Kong Polytechnic University, University of California, Santa Barbara, and National University of Singapore have published a new technical paper. The research focuses on achieving low contact resistance and high current density in ballistic p-type transistors based on oxygen-doped tungsten diselenide monolayers. [1]

The research team demonstrated methods to push two-dimensional transistors toward integration in advanced complementary metal-oxide-semiconductor manufacturing. The technical paper details performance improvements in high-performance p-type monolayer devices. [1]

Electrical resistance measures opposition to electric current flow, which is critical in transistor contact scaling. FinFET technology previously provided higher current density and faster switching times than planar CMOS by using multigate fins on the silicon substrate. [2][3]

Reducing contact resistance in monolayer materials addresses a key barrier to deploying two-dimensional channels in future semiconductor production nodes. [1]